This invention deals with TTL circuitry, and in particular to a TTL circuit having increased transient drive for rapid switching between two logical states.
Transistor-Transistor-Logic (TTL) has been used for construction of digital circuits. Digital circuits operate by switching signals between two discrete levels, a logical one or "high" and a logical zero or "low". In order to qualify as a logical zero, a voltage level must not be greater than a predetermined voltage level. When individual TTL integrated circuits are connected on a printed circuit board, for example, the logical zero state is indicated by an output low voltage (VOL) of less than or equal to 0.4 volts, and a logical one is indicated by an output high voltage (VOH) of greater than or equal to 2.4 volts. Within integrated circuits themselves, these VOL and VOH voltages may be designed to have different predetermined values.
Of primary importance in digital circuits is the speed at which transitions occur between logic states, i.e., the speed at which a particular signal can transition from a logical one state to a logical zero state, and vice versa.
FIG. 1a is a schematic diagram of a typical TTL output stage. A digital input signal is applied to input terminal IN1 which controls the operation of phase splitter transistor Q1. Transistor Q1 is termed a "phase splitter" transistor because the digital value on its emitter becomes equivalent to the digital value applied to terminal IN1, and the digital value on the collector of transistor Q1 has the inverse logical value of the input signal applied to input terminal IN1. With a logical one input signal applied to input terminal IN1, transistor Q1 turns on providing current to the emitter of transistor Q1. This current causes output pulldown transistor Q4 to turn on, thereby pulling output terminal OUT1 to ground through the emitter-collector path of conducting pulldown transistor Q4. Simultaneously, the relatively low voltage on the collector of transistor Q1 is insufficient to forward bias the Darlington pair formed by transistors Q2 and Q3, and thus transistors Q2 and Q3 do not source current to output terminal OUT1 when the input signal received on input lead IN1 is a logical one.
Conversely, when the input signal applied to input lead IN1 is a logical zero, transistor Q1 is off, thereby not providing base drive to pulldown transistor Q4. This causes transistor Q4 to be turned off and not sink current from output terminal OUT1 to ground. Simultaneously, the voltage at the collector of transistor Q1 is high since transistor Q1 is not conducting, and causes the Darlington pair formed by transistors Q2 and Q3 to turn on, thereby sourcing current from positive voltage supply VCC to output terminal OUT1.
While the static operation of the circuit of FIG. 1a described above is relatively simple, dynamic operation (i.e., during switching) is more complex. During the transition from a logical zero output signal to a logical one output signal, transistor Q4 must turn off. For this purpose, resistor R2 causes the charge on the base of transistor Q4 to dissipate, thereby allowing output pulldown transistor Q4 to turn off relatively rapidly. Other techniques for discharging the base of transistor Q4 have also been used in the prior art.
Conversely, during the transition from a logical one output signal to a logical zero output signal in response to a logical zero to a logical one transition of the input signal applied to input terminal IN1, transistor Q1 turns on, and transistor Q4 turns on. However, prior to the turn on of transistor Q4, sufficient current must be provided by phase splitter transistor Q1 in order to charge the base of transistor Q4 to cause it to turn on. Some of this current is undesirably consumed by resistor R2 which, as previously described, is essential in order to cause relatively rapid turn off of transistor Q4. Thus, in the circuit of FIG. 1a, there is a trade off between the speed at which transistor Q4 can turn off, and the speed at which transistor Q4 can turn on. There is also a trade off between power consumption and switching speed: higher currents through transistor Q1 allow the base of transistor Q4 to charge more rapidly.
Another prior art circuit is shown in FIG. 1b, which includes all of the elements of the circuit of FIG. 1a, identified with similar numerals. In the circuit of FIG. 1b, feedback diode D1 is provided having its cathode connected to output lead OUT1 and its anode connected to the base of transistor Q10. When the output signal on output lead OUT1 goes low due to conduction of pull-down transistor Q4, feedback diode D1 becomes forward biased, thereby reducing the signal applied to the base of transistor Q10, which in turn reduces the drive available to pull-down transistor Q4. This voltage feedback provided by the addition of feedback diode D1 and transistor Q10 reduces the drive to pull-down transistor Q4 when the output signal on terminal OUT1 reaches the logical zero level, thereby keeping transistor Q10 operating in the linear mode, allowing transistor Q10 to provide additional drive in response to increasing loads on output terminal OUT1. However, this circuit unfortunately has some instability in the form of transient ringing of the output signal on output terminal OUT1 due to the phase lag of signals propagated through the feedback loop provided by feedback diode D1. Transient ringing causes the output signal to vary in amplitude, making it difficult to determine its intended state (i.e., logical one of logical zero).
Another prior art circuit is shown in FIG. 1c, which includes all of the elements of the circuit of FIG. 1a, identified with similar numerals. The circuit of FIG. 1c includes two phase splitter transistors Q1a, Q1band also includes transistor Q5 having its collector connected to voltage supply VCC through resistor R10, its base connected to the collector of phase splitter transistor Q1, and its emitter connected to input terminal IN1. Thus, transistor Q5 provides additional drive current to input lead IN1 in response to a high to low transition of the output signal on output lead OUT1. However, during this transition, the input signal on input lead IN1 is making a transition from low to high, and thus the additional drive provided by transistor Q5 decreases as the input signal on input lead IN1 increases, midway through the high to low transition of the output signal. This is, of course, undesirable, since the additional drive current is not provided during the entire transition time.
Thus, prior art TTL circuits suffer from problems with the speed at which transitions between logic states can occur, and the power requirements of such circuits.